The present invention relates generally to a method of forming solder bumps on an integrated circuit device, typically a semiconductor chip, for mounting the device on a carrier in a flip-chip configuration.
Flip-chip bonding is a well-known method of interconnecting integrated circuit devices (also known as semiconductor chips) to carriers. In the flip-chip bonding process, solder bumps are formed on interconnection pads on the active side of an integrated circuit device. The chip is then inverted and bonded to a carrier with a matching set of interconnection pads. The solder bumps form solder joints between the chip and the carrier and provide both mechanical and electrical interconnections.
Typically, the solder bumps are formed on integrated circuit devices by electrolytically plating solder bump precursor structures, typically a PbSn solder, through a photoresist mask. A layer of photoresist is first applied to the active side of a silicon wafer, on which an array of integrated circuit devices have been formed, and cured. Each integrated circuit device is provided with an array of interconnection pads on the active side and the surface of the interconnection pads are provided with finishing metal structure or Under Ball Metallurgy (xe2x80x9cUBM,xe2x80x9d also known as Ball Limiting Metallurgy). The photoresist is then exposed with a pattern of the integrated circuit devices"" UBM pads using a photo mask, and developed, resulting in a pattern of holes with a desired diameter exposing the UBM pads on the integrated circuit devices. Next, the solder bump precursor structure is electro-plated onto the exposed UBM pads and the photoresist layer is removed with a chemical stripping process leaving behind an array of columnar solder bump precursor structures on the integrated circuit devices. Finally, the solder bump precursor structures are reflowed to form substantially spherical solder bumps. The particular reflow process is determined by the particular composition of the solder utilized.
Two of the commonly practiced methods for applying the photoresist layer on the semiconductor wafer are a Dry Film Resist (xe2x80x9cDFRxe2x80x9d) process and a spin-coating process. In the DFR process, a dry photoresist film (100 to 125 microns thick) is laminated onto the wafer before it is exposed and developed. In the spin-coat process, a thin film of photoresist is first coated on to the wafer, then, exposed and developed to form a plating mask for the solder bump precursor structure.
One drawback of the solder bump flip-chip bonding technology, particularly when the integrated circuit devices are bonded to polymer printed circuit carriers such as epoxyglass, is the solder joint reliability concerns resulting from the mismatch of the coefficients of thermal expansion (xe2x80x9cCTExe2x80x9ds) between the polymer printed circuit carriers and the integrated circuit devices. Typical silicon based integrated circuit devices have a CTE of about 3 ppm/deg. C, in contrast to the CTE of polymer printed circuit carriers, which is about 16 to 26 ppm/deg. C. Because of this mismatch in CTEs, the solder joints experience cyclical stress during the life of its use, as the integrated circuit device and polymer printed circuit carrier assembly is exposed to many thermal excursions as the chip is powered on and off, possibly resulting in fatigue failures of the solder joints.
It is well known in the semiconductor packaging industry that the fatigue reliability of the solder joints in flip-chip bonding application can be improved by increasing the height of the solder joints thereby reducing the strain observed at the solder joints. Since the height of a solder bump is a function of the volume of solder structure plated on a UBM pad and the diameter of the given UBM pad, one method of increasing the solder bump height is to continue plating the solder beyond the thickness of the photoresist plating mask during the solder bump precursor forming process forming a mushroom-shaped extra solder structure on the plating mask. This extra solder increases the volume of the resulting solder bump and, thus, the height of the solder bump. But, the mushroom-shaped as-plated solder structure has a tendency to trap undissolved photoresist material under the mushroom-shaped overhang during the photoresist stripping process. Such photoresist residue can cause solder non-wet or partial-wet joint defects during the flip-chip bonding process. Furthermore, adjacent mushroom-shaped overhangs may contact one another and cause electrical shorting problems if too much additional solder is deposited.
Another possible method of increasing the height of the solder bump is to increase the thickness of the photoresist plating mask so that taller interim solder structures may be plated without the formation of a mushroom-shaped structure. But, as the thickness of the phororesist plating mask is increased, there is a greater tendency for residual photoresist to be left behind in the openings during the photoresist development step.
Another conventional method of forming taller solder bumps is to plate more solder onto larger UBM pads. But increasing the diameter of the UBM pads is not particularly desirable because the trend in the industry is to reduce the pitch of the solder bump arrays in order to accommodate higher level of circuit integration in integrated circuit devices that require greater interconnection densities.
Therefore, a need exists for an improved solder-bump deposition process that will provide increased solder-bump height without the concerns discussed above.
The present invention provides a method of forming solder bumps on an integrated circuit device for flip-chip bonding. First a photoresist layer is applied over the integrated circuit device. The photoresist layer is patterned with holes aligned over interconnection pads on the integrated circuit device using a photolithography process. Next, a first layer of solder structures is deposited into the patterned holes in the photoresist layer filling the patterned holes with solder. A second layer of solder structures is deposited on top of the first layer of solder structures in a pattern aligned with the patterned holes in the photoresist layer. The second layer of solder structures have smaller diameter than the first layer of solder structures resulting in two-level solder bump precursor structures at the patterned hole locations. The photoresist layer is then removed leaving the two-level solder precursor structures standing. Finally, the two-level solder precursor structures are reflowed to form substantially spherical solder bumps.
In the process described above according to an embodiment of the invention, the second layer of solder may be deposited by printing through a screen or a stencil. In another embodiment of the present invention, the second layer of solder may be deposited by an electroplating process. In the latter case, the process would typically require a formation of another photoresist plating mask layer on top of the first photoresist layer. This second layer of photoresist plating mask would be formed in the same manner as the first photoresist layer with one key difference being that the second photoresist solder mask layer would be formed with patterned holes having smaller diameter than the patterned holes in the first photoresist plating mask layer.
Using the process of the present invention, the as-reflowed solder bump height may be increased by depositing additional solder without creating the mushroom-like solder overhanging structure associated with the prior art processes discussed above. Because the second layer of solder structures have smaller diameter than the first layer of plated solder structures, the second layer of solder does not have any portions that overhang the solder bump precursor structures formed by the first layer of solder. And without the overhanging structure, any residual photoresist concerns resulting from incomplete removal of photoresist material trapped under the overhanging structure is eliminated.
The method of the present invention is also advantageous over the alternative process of depositing more solder on larger UBM pads. With the process of the present invention, as-reflowed height of solder bumps may be increased without increasing the diameter of UBM pads. Consequently, compared to the conventional process of depositing more solder on to larger UBM pads to achieve taller as-reflowed solder bumps, the incremental increase in the solder volume required to achieve the same incremental increase in the as-reflowed solder bump height is less.
The invention will now be illustrated in some specific embodiments in accordance with the invention.